Modern electronic devices such as a notebook computer comprise a variety of memories to store information. Memory circuits include two major categories. One is volatile memories; the other is non-volatile memories. Volatile memories include random access memory (RAM), which can be further divided into two sub-categories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they will lose the information they store when they are not powered. On the other hand, non-volatile memories can keep data stored on them. Non-volatile memories include a variety of sub-categories, such as electrically erasable programmable read-only memory (EEPROM) and flash memory.
SRAM cells may comprise different numbers of transistors. According to the total number of transistors in an SRAM cell, the SRAM cell may be referred to as a six-transistor (6-T) SRAM, an eight-transistor (8-T) SRAM, and the like. SRAM cells are arranged in rows and columns. An SRAM cell is selected during either a READ operation or a WRITE operation by selecting its row and column. The row and column to be selected are determined by a binary code. For example, a 64 Kb memory chip may comprise a 16-bit binary code controlling the WRITE and READ operation. More particularly, the 16-bit binary code is split into two separate 8-bit binary codes for selecting a row and a column respectively. The 64 Kb memory chip may further comprise a row decoder and a column decoder. In response to an 8-bit code, the row decoder is able to generate 28 outputs, which comes to 256 outputs. Likewise, the column decoder is able to generate another 28 outputs. By enabling an output from the row decoder and an output from the column decoder, an SRAM cell can be selected from a memory cell matrix having 256 rows and 256 columns.
Each column of an SRAM cells is connected to both a bit-line (BL) and the inverse of BL ( BL). A data latch of each SRAM cell is used to store a single bit. Both BL and BL are used to control the operation of reading a bit from or writing a bit into the SRAM cell. For example, in an SRAM WRITE operation, a logic state “1” stored in a data latch of the SRAM cell can be reset by setting BL to “0” and BL to “1”. Furthermore, two pass-gate transistors connected between the data latch and BL and BL are controlled by a word line. In response to a binary code from the row decoder, a word line coupled to the SRAM cell to be written is asserted so that the data latch is selected to proceed to a WRITE operation. During a WRITE operation, one storage node of the data latch is discharged by BL to “0” and the other storage node of the data latch is charged by BL to “1”. As a result, the new data logic “0” is latched into the SRAM cell.
In a READ operation, both BL and BL of an SRAM cell are pre-charged to a voltage approximately equal to the operating voltage of the memory bank in which the SRAM cell is located. In response to a binary code from the row decoder, a word line coupled to the SRAM cell to be read is asserted so that the data latch is selected to proceed to a READ operation. During a READ operation, through a turned on pass-gate transistor, one bit line coupled to the storage node storing a logic “0” is discharged to a lower voltage. Meanwhile, the other bit line remains the pre-charged voltage because there is no discharging path between the other bit line and the storage node storing a logic “1”. The differential voltage between BL and BL (approximately in a range from 50 to 100 mV) is detected by a sense amplifier. Furthermore, the sense amplifier amplifies the differential voltage and reports the logic state of the memory cell via a data buffer.
As semiconductor technologies evolve, the operating voltages of SRAM memory chips are further reduced. The decrease of the operating voltages can reduce SRAM cell power consumption. However, the lower operating voltages of SRAM cells may reduce WRITE and READ margins to a low level. Such a low level can cause less reliable WRITE and READ operations.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.